DSP of the second kind

DSP of the Second Kind (1995-2005)
The goal of this section, is an historical perspective covering the time when DSPs became CPUs and vice versa.

Background

We are now in 1996 and for the last couple of years DSP is fashionable in Silicon valley. To complicate things further, DSP is just seen as a subset of the shining keyword of the 1990's: "MULTIMEDIA"."TA!DA!" Pretty much all processor vendors are preparing something. A good summary of that time is found in Jeff Bier's [ref 1 and 2].

Description

Roughly speaking there were 3 and a half types, here classified by interest order.

1. Add a DSP COP to a CPU (or more likely a MCU).
2. Add a DSP extension to an existing CPU ISA
3. Start from scratch and build a completely new architecture. It can be:
1. a DSP based on RISC principle (ZSP)
2. a DSP based on more RISCY than Thou Principle(C6x)
3. a RISC CPU equally good at DSP (TriCore)
4. a DSP with a register file 
4. Multimedia processors (MM)
1. We will not mention MM further, except that for the sake of simplification we will put Pentium MMX  in this category instead of ISA extension. Remember that we are speaking about DSPs.
5. Not considered: dual-core platforms such as consisting of a DSP core  plus a CPU core.

When looking at the 3 remaining categories they can all be grouped under DSP extensions.Category 1 and 2 differ only by the level of integration.Category 1 integrates DSP as  a COP, category 2 integrates DSP as a separate execution unit or as a fatter data path.  In the end it all became implementation details. Funnily enough, category 3 (the new architectures) all started monolithic but under the influence of the deconstruction school (TenSilica) many came up with the concept of simpler core + extension.
We can also lamely argue that a C64x can be seen as a CPU (1 cluster + 3 simplest execution units (EU) ) or a powerful DSP ( 2 clusters with all 4 EUs).

Category 1- DSP COP

Largely obsoleted by category 2 and 3, we will mention a few products:

1. SH-DSP (1996) had a COP added to the the SH-3 core " good classic model"
2. ARM Piccolo (1997) , was architecturally identical  but with the bonus of original solutions to some basic problems. (To be studied in details)
3. Siemens C166/ST10 MAC (1998) started as a COP and finished as fully integrated ST Super10.
4. And later, for instance...Massana Filu which was a piece of IP ( a COP). to be attached to a host. 
5. We will not mention here the Tensilica Vectra or similar which are filed under Vector Processor.  

Category 2- DSP extensions to CPU

Here are examples of DSP extensions to common CPU ISA.  Note that not all of them are "Q format" types and are more commonly classified as MM extensions(*VP*). From our perspective, the difference between the twos are more understood in terms of DSP generation.

1. PowerPC
1. Altivec and variants (*VP*)
2. MPC8xx  DSP addendum (MPC8xxRMAD Rev.0.1., 10/2003)
2. ARM (we are a bit lost here)
1. Move
2. Neon (*VP*)
3. MM extensions
4. SIMD
5. ARM9E
6. Xscale WMMX , WMMX2
3. MIPS
1. Lexra DSP extensions
2. MIPS DSP extensions
4. Coldfire DSPon
5. Hitachi MM extensions
6. TenSilica Vectra, VectraLX (*VP*)
7. ARC SIMD at MPR05
8. PIC MCU adds DSP (2005)
9. Intel SSE4
   
10. Sparc, HP --> see Ruby Lee, AMD, Alpha, MIPS Madmax

Categorie 3- New DSP Architectures

Further sub categorized as

1. New CPU
1. The unique illustration as such is TriCore (1996). 
2. New DSP   
1. Blackfin (1998) presented itself as an hybrid  but really a DSP (hey 40-bit native register width, give you away)
2. Tiger Sharc (1999)
3. Starcore (1999)
4. TI C62x (1997) became C64x(2000) then C66 (2010)
1. And of course C67
5. New name: ZSP (1997)
6. tons of other hopefuls
7. We will not mention the Infineon Carmel and the DSP group family (see "revenge of the trees" and "the last honest DSP" in chapter DSP of the First Kind). 

Category (outside): dual-core platforms

-> see platforms, Multi-Core.

• For the record
• 68356
• Dual core consisting of a DSP  plus a CPU (typ: ARM7 + OAK)

References

1. BDTI  “DSP on General Purpose Processors—An Overview”, presentation to MicroDesign Resources dinner meeting, January 1997. 
2. --> giving rise to the BDT Guide - DSP on GP CPU (1997)
3. also comparing BDTI guide 2004 and 1995 reveals the amount of the evolution.
4. BDTI guide on TriCore (not available)
5. BDTI guide on StarCore 
6. Multiple press vulgarus articles on "hybrid", C compilation and register files.
7. The many TI VLIW white papers