Bit Slice BB

Bit Slice Building Blocks

The goal of this section is to cover a quick history of bit slice logic, the impact on fully integrated DSP of the first generation and to provide the methodology for today COPS.

Background

See references AMD Mick and Brick, blakeley etc..

Description

Bit slice logic was not only a series of components but most of all a technique to build a General Purpose (GP) computer and best of all a GP DSP.
Basically any DSP can be build from 3 units (or BB):

• PCU: Program control Unit
• DAU: Data Arithmetic Unit
• AGU: Address Generation Unit

The way the 3 units are connected does not vary. What will vary is the features of each unit, the number (and width) of buses, the number of memories and the microcode.


Program Control Unit (PCU)
Its function is to fetch instructions and to decode them before dispatching to the respective units. In the bit slice model the decoding is not part of the PCU. Since the instructions are very wide and monolithic, there is an intermediate level (the microprogram store). A good example of PCU is the 29110 sequencer from the original AMD 29 bit-slice family but all DSPs have a section describing the PCU. This section goes by various names. 
 

Data Arithmetic Unit (DAU)
The DAU goes by many names and many types. The original AMD29x family had the 2901 called RALU (for register file + ALU) . And because we were processing signals, we added a multiplier which gave rise to the 2 standard  topologies (multiplier in series and parallel). Introduction of GP DSPs kind of standardized on the 16*16 + 40 structure. With the 90s and the vulgarisation of computer architecture, first came the name IP (Integer Processing), then the parallel topology as the units were all attached to the Register File, then new type of units (Bit Manipulation Unit, Bit Field unit, Shuffle), then duplication of units (super scalar) and sub word parallelism.
Today, the DAU is where most of the action is. Especially since our goal is to implement Matlab functions.   

Address Generation Unit (AGU)
The AGU  is a bit of the poors man BB of the bit slice family. For instance, the original AMD family did not have any (it was simpler to implement one with a RALU). This is still partially true today, an AGU is a degenerated ALU (1) but as anything dealing with memories it should not be underestimated .
See here for more details.


(1) In the simplistic model of computer architecture there is no AGU. Firstly there is no load/store parallelism and moreover there is a unified register file (see ARM7, ARM9, MIPS, PPC, etc..). {obviously I do not go into superscalar here}.