DSP architecture today

The goal of this section is to put in one place any architecture bits and pieces which are interesting for this blog. 

The generic design methods                                                                                                  

• Vector processing 
• SIMD, swp (sub-word parallelism), multi lanes, packed arithmetic... 
• where to stop? 256? 1024?
• why stop at 1K? Matlab row vectors, cln vectors, arrays are a magnitude higher 
• Minimum parallelism= 64K 
• simd of 16  x 16 clusters x 16 cores  x 16 modules 
• Golden ratio (x4, x16, x64, x256) 

On My watch                                                                                                                          

• "ASPI world"
• Andre Duhon
• FCCM
• Xilinx at Large
• GPU
• Matlab and GPU
• Coda
• Deep packet searching
• Hot Chips
• TenSilica cores and domain specific platforms, 
• Cadence

They still Matters                                                                                                                  

• ARM Cortex A - family and evolution
• how far will they go with speculation? 
• repeating the same mistakes in a new way?
• Intel ecosystem
• Altera integration
• TI Platforms evolution 
• replacing DSP core with hardwired COP

Lessons Learnt                                                                                                                         

• NPU

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